88 search results - page 11 / 18 » On load latency in low-power caches |
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
JSA
2006
14 years 9 months ago
2006
Multimedia applications in general and video processing, such as the MPEG4 Visual stream decoders, in particular are increasingly popular and important workloads for future embedd...
HPCA
1997
IEEE
15 years 1 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
ASPLOS
2004
ACM
15 years 2 months ago
2004
ACM
This paper explores a new technique called coherence decoupling, which breaks a traditional cache coherence protocol into two protocols: a Speculative Cache Lookup (SCL) protocol ...
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ICS
2007
Tsinghua U.
15 years 3 months ago
2007
Tsinghua U.
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...