305 search results - page 54 / 61 » On modeling top-down VLSI design |
VLSID
2009
IEEE
15 years 10 months ago
2009
IEEE
The current paradigm of using Cu interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck in ultra-deep submicron (UDSM) technologies. C...
68
Voted
DFT
2003
IEEE
15 years 3 months ago
2003
IEEE
In the last years, new requirements in terms of vehicle performance increased significantly the amount of on-board electronics, thus raising more concern about safety and fault to...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
SOFSEM
2005
Springer
15 years 3 months ago
2005
Springer
d Abstract) Lubomir Torok Institute of Mathematics and Computer Science Slovak Academy of Sciences Severna 5, 974 01 Banska Bystrica, Slovak Republic 3-dimensional layout of graph...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...