21 search results - page 4 / 5 » On optimal temporal locality of stencil codes |
ASPLOS
1996
ACM
13 years 10 months ago
1996
ACM
This paper analyzes and quantifies the locality characteristics of numerical loop nests in order to suggest future directions for architecture and software cache optimizations. Si...
GLVLSI
2005
IEEE
13 years 12 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
LCTRTS
2005
Springer
13 years 11 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
ICCS
2005
Springer
13 years 11 months ago
2005
Springer
Abstract. The increasing gap of processor and main memory performance underlines the need for cache-optimizations, especially on memoryintensive applications. Tools which are able ...
ICS
1999
Tsinghua U.
13 years 10 months ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...