46 search results - page 4 / 10 » On pipelining dynamic instruction scheduling logic |
86
Voted
IPPS
2006
IEEE
15 years 4 months ago
2006
IEEE
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
83
Voted
ICCD
2006
IEEE
15 years 7 months ago
2006
IEEE
This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction sc...
ISCA
2011
IEEE
14 years 1 months ago
2011
IEEE
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
113
Voted
ASPLOS
2004
ACM
15 years 3 months ago
2004
ACM
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
93
Voted
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...