46 search results - page 5 / 10 » On pipelining dynamic instruction scheduling logic |
91
Voted
CF
2005
ACM
15 years 6 days ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
73
Voted
ISCA
1997
IEEE
15 years 2 months ago
1997
IEEE
Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, t...
75
Voted
JSA
2008
14 years 10 months ago
2008
Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating arch...
89
Voted
ICS
2005
Tsinghua U.
15 years 3 months ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
90
Voted
ISLPED
2003
ACM
15 years 3 months ago
2003
ACM
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...