30 search results - page 4 / 6 » On scheduling dags to maximize area |
DATE
2000
IEEE
15 years 4 months ago
2000
IEEE
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
CSI
2007
14 years 11 months ago
2007
Recently, much attention has been given to the need to endow industrial communication networks used in real-time systems with flexible scheduling. This allows control systems to a...
ASPDAC
1995
ACM
15 years 3 months ago
1995
ACM
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
128
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FPGA
2010
ACM
14 years 12 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
113
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INFOCOM
2010
IEEE
14 years 10 months ago
2010
IEEE
—With the convergence of multimedia applications and wireless communications, there is an urgent need for developing new scheduling algorithms to support real-time traffic with ...