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» On software design for stochastic processors
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IPPS
2009
IEEE
15 years 8 months ago
Using hardware transactional memory for data race detection
Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
Shantanu Gupta, Florin Sultan, Srihari Cadambi, Fr...
EMSOFT
2007
Springer
15 years 8 months ago
The revenge of the overlay: automatic compaction of OS kernel code via on-demand code loading
There is increasing interest in using general-purpose operating systems, such as Linux, on embedded platforms. It is especially important in embedded systems to use memory effici...
Haifeng He, Saumya K. Debray, Gregory R. Andrews
HOTI
2005
IEEE
15 years 7 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
ESTIMEDIA
2005
Springer
15 years 7 months ago
Scratchpad Sharing Strategies for Multiprocess Embedded Systems: A First Approach
Portable embedded systems require diligence in managing their energy consumption. Thus, power efficient processors coupled with onchip memories (e.g. caches, scratchpads) are the...
Manish Verma, Klaus Petzold, Lars Wehmeyer, Heiko ...
LCPC
2005
Springer
15 years 7 months ago
Titanium Performance and Potential: An NPB Experimental Study
Titanium is an explicitly parallel dialect of JavaTM designed for high-performance scientific programming. It offers objectorientation, strong typing, and safe memory management...
Kaushik Datta, Dan Bonachea, Katherine A. Yelick