964 search results - page 179 / 193 » On software design for stochastic processors |
122
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ISPASS
2007
IEEE
15 years 8 months ago
2007
IEEE
— The design trend towards CMPs has made the simulation of multiprocessor systems a necessity and has also made multiprocessor systems widely available. While a serial multiproce...
115
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HIPEAC
2007
Springer
15 years 8 months ago
2007
Springer
In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in the issue queue. Instructions are then issued by the back-end execution core. T...
119
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LCTRTS
2007
Springer
15 years 8 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
133
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LCTRTS
2007
Springer
15 years 8 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
100
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CGO
2010
IEEE
15 years 7 months ago
2010
IEEE
Cross-core application interference due to contention for shared on-chip and off-chip resources pose a significant challenge to providing application level quality of service (Qo...