96 search results - page 10 / 20 » On test coverage of path delay faults |
118
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ISCAS
2007
IEEE
15 years 6 months ago
2007
IEEE
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
110
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ATS
2003
IEEE
15 years 5 months ago
2003
IEEE
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
89
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VTS
1996
IEEE
15 years 3 months ago
1996
IEEE
This paper presents an innovative method for inserting test points in the circuit-under-test to obtain complete fault coverage for a specified set of test patterns. Rather than us...
97
Voted
ATS
2005
IEEE
15 years 5 months ago
2005
IEEE
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
71
Voted
DDECS
2007
IEEE
15 years 3 months ago
2007
IEEE
A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this r...