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» On test coverage of path delay faults
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ET
2000
145views more  ET 2000»
14 years 9 months ago
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
Jaan Raik, Raimund Ubar
TCAD
2008
114views more  TCAD 2008»
14 years 9 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty
DATE
2008
IEEE
109views Hardware» more  DATE 2008»
15 years 4 months ago
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
Jeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad...
INFSOF
2007
104views more  INFSOF 2007»
14 years 9 months ago
A state-based approach to integration testing based on UML models
: Correct functioning of object-oriented software depends upon the successful integration of classes. While individual classes may function correctly, several new faults can arise ...
Shaukat Ali, Lionel C. Briand, Muhammad Jaffar-Ur ...
DAC
1994
ACM
15 years 1 months ago
Dynamic Search-Space Pruning Techniques in Path Sensitization
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
João P. Marques Silva, Karem A. Sakallah