Sciweavers

96 search results - page 15 / 20
» On test coverage of path delay faults
Sort
View
89
Voted
VTS
1997
IEEE
86views Hardware» more  VTS 1997»
15 years 1 months ago
Methods to reduce test application time for accumulator-based self-test
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
Albrecht P. Stroele, Frank Mayer
70
Voted
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
15 years 3 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
15 years 2 months ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
79
Voted
ICSM
2008
IEEE
15 years 3 months ago
Quota-constrained test-case prioritization for regression testing of service-centric systems
Test-case prioritization is a typical scenario of regression testing, which plays an important role in software maintenance. With the popularity of Web Services, integrating Web S...
Shan-Shan Hou, Lu Zhang, Tao Xie, Jiasu Sun
ITC
2003
IEEE
93views Hardware» more  ITC 2003»
15 years 2 months ago
Hybrid Multisite Testing at Manufacturing
This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisi...
Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lomb...