96 search results - page 16 / 20 » On test coverage of path delay faults |
ATS
2000
IEEE
15 years 1 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on Evolutionary Algorithms. In c...
DFT
2002
IEEE
15 years 2 months ago
2002
IEEE
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
62
Voted
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
The impact of test conditions on the detectability of open defects is investigated. We performed an inductive fault analysis on representative standard gates. The simulation resul...
DSD
2006
IEEE
15 years 3 months ago
2006
IEEE
Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern genera...