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» On test coverage of path delay faults
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VTS
1997
IEEE
73views Hardware» more  VTS 1997»
15 years 1 months ago
Obtaining High Fault Coverage with Circular BIST Via State Skipping
Despite all of the advantages that circular BIST ofsers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has se...
Nur A. Touba
ASPDAC
2004
ACM
112views Hardware» more  ASPDAC 2004»
15 years 2 months ago
Longest path selection for delay test under process variation
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, We...
ICCAD
2006
IEEE
134views Hardware» more  ICCAD 2006»
15 years 6 months ago
A delay fault model for at-speed fault simulation and test generation
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
15 years 6 months ago
Statistical path selection for at-speed test
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chan...
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
15 years 3 months ago
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, S...