96 search results - page 6 / 20 » On test coverage of path delay faults |
80
Voted
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
This paper presents a case-study of delay defect screening applied to Fujitsu 2.16GHz SPARC64 microprocessor. A nonrobust delay test is used while each test vector is compacted to...
JISE
2000
14 years 9 months ago
2000
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...
74
Voted
VTS
1998
IEEE
15 years 1 months ago
1998
IEEE
This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators TPGs. Bit transition maximiz...
75
Voted
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
The first non-enumerative framework for diagnosing path delay faults using zero suppressed binary decision diagrams is introduced. We show that fault free path delay faults with ...
90
Voted
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...