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» On test coverage of path delay faults
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VTS
1996
IEEE
112views Hardware» more  VTS 1996»
15 years 1 months ago
Optimal voltage testing for physically-based faults
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
Yuyun Liao, D. M. H. Walker
90
Voted
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
15 years 1 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler
ITC
2000
IEEE
80views Hardware» more  ITC 2000»
15 years 1 months ago
Test program synthesis for path delay faults in microprocessor cores
Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
VLSID
1995
IEEE
112views VLSI» more  VLSID 1995»
15 years 1 months ago
An efficient automatic test generation system for path delay faults in combinational circuits
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...