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» On test coverage of path delay faults
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118
Voted
ITC
1993
IEEE
148views Hardware» more  ITC 1993»
15 years 3 months ago
DELTEST: Deterministic Test Generation for Gate-Delay Faults
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
Udo Mahlstedt
MEMOCODE
2007
IEEE
15 years 6 months ago
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
Stephan Eggersglüß, Görschwin Fey,...
88
Voted
ET
2010
98views more  ET 2010»
14 years 10 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...
96
Voted
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
15 years 3 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
15 years 4 months ago
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
Xiao Liu, Yubin Zhang, Feng Yuan, Qiang Xu