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CGO
2005
IEEE
15 years 5 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
MICRO
2003
IEEE
143views Hardware» more  MICRO 2003»
15 years 5 months ago
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik ...
ICC
2007
IEEE
127views Communications» more  ICC 2007»
15 years 6 months ago
Adaptive-Buffer Power Save Mechanism for Mobile Multimedia Streaming
— Wireless networks are becoming a part of everyday life for many people. When a mobile device has wireless LAN capability, multimedia content can be streamed over a wireless net...
Janet Adams
MICRO
2008
IEEE
136views Hardware» more  MICRO 2008»
15 years 6 months ago
Power to the people: Leveraging human physiological traits to control microprocessor frequency
Any architectural optimization aims at satisfying the end user. However, modern architectures execute with little to no knowledge about the individual user. If architectures could...
Alex Shye, Yan Pan, Benjamin Scholbrock, J. Scott ...
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches
In recent years, several alternative devices have been proposed to deal with inherent limitation of conventional CMOS devices in terms of scalability at nanometer scale geometry. ...
Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab