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ERSA
2003
118views Hardware» more  ERSA 2003»
15 years 1 months ago
A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA
The availability of SiGe HBT devices has opened a door for Gigahertz FPGAs. However, the large device power consumption limits its scale. In order to solve this problem, a Multipl...
Jong-Ru Guo, Chao You, Michael Chu, Kuan Zhou, You...
CE
2005
58views more  CE 2005»
14 years 11 months ago
Does ICT contribute to powerful learning environments in primary education?
In powerful learning environments, rich contexts and authentic tasks are presented to pupils. Active, autonomous and co-operative learning is stimulated, and the curriculum is ada...
Ed Smeets
MICRO
2012
IEEE
231views Hardware» more  MICRO 2012»
13 years 2 months ago
What is Happening to Power, Performance, and Software?
The past 10 years have delivered two significant revolutions. (1) Microprocessor design has been transformed by the limits of chip power, wire latency, and Dennard scaling—leadi...
Hadi Esmaeilzadeh, Ting Cao, Xi Yang, Stephen Blac...
DAC
2006
ACM
16 years 25 days ago
Leakage power reduction of embedded memories on FPGAs through location assignment
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
Yan Meng, Timothy Sherwood, Ryan Kastner
ASPDAC
2009
ACM
127views Hardware» more  ASPDAC 2009»
15 years 6 months ago
Timing driven power gating in high-level synthesis
- The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock ...
Shih-Hsu Huang, Chun-Hua Cheng