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DAC
2008
ACM
16 years 27 days ago
Many-core design from a thermal perspective
Air cooling limits have been a major design challenge in recent years for integrated circuits. Multi-core exacerbates thermal challenges because power scales with the number of co...
Wei Huang, Mircea R. Stan, Karthik Sankaranarayana...
DAC
2005
ACM
16 years 26 days ago
System-level energy-efficient dynamic task scheduling
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time...
Jianli Zhuo, Chaitali Chakrabarti
DAC
2006
ACM
16 years 26 days ago
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty
The gain-based technology mapping paradigm has been successfully employed for finding minimum delay and minimum area mappings. However, existing gain-based technology mappers fail...
Ashish Kumar Singh, Murari Mani, Ruchir Puri, Mich...
DATE
2009
IEEE
153views Hardware» more  DATE 2009»
15 years 6 months ago
TRAM: A tool for Temperature and Reliability Aware Memory Design
— Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system’s power dissipation, area and reliability. In th...
Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurd...
ICESS
2007
Springer
15 years 6 months ago
Sleep Nodes Scheduling in Cluster-Based Heterogeneous Sensor Networks Using AHP
Abstract. Wireless sensor networks (WSNs) are comprised of energy constrained nodes. This limitation has led to the crucial need for energy-aware protocols to produce an efficient ...
Xiaoling Wu, Jinsung Cho, Brian J. d'Auriol, Sungy...