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» On the Adders with Minimum Tests
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94
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ASYNC
2005
IEEE
96views Hardware» more  ASYNC 2005»
15 years 5 months ago
GasP Control for Domino Circuits
We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare...
Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Iv...
105
Voted
ET
1998
52views more  ET 1998»
14 years 11 months ago
Scalable Test Generators for High-Speed Datapath Circuits
This paper explores the design of efficient test sets and test-pattern generators for online BIST. The target applications are high-performance, scalable datapath circuits for whi...
Hussain Al-Asaad, John P. Hayes, Brian T. Murray
ATS
2001
IEEE
137views Hardware» more  ATS 2001»
15 years 3 months ago
Compaction Schemes with Minimum Test Application Time
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
Ozgur Sinanoglu, Alex Orailoglu
79
Voted
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
15 years 5 months ago
Structural Testing Based on Minimum Kernels
Structural testing techniques, such as statement and branch coverage, play an important role in improving dependability of software systems. However, finding a set of tests which...
Elena Dubrova
ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
15 years 3 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich