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» On the Architecture of System Verification Environments
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ICCAD
1994
IEEE
122views Hardware» more  ICCAD 1994»
15 years 4 months ago
An enhanced flow model for constraint handling in hierarchical multi-view design environments
In this paper we present an enhanced design flow model that increases the capabilities of a CAD framework to support design activities on hierarchical multi-view design descriptio...
Pieter van der Wolf, K. Olav ten Bosch, Alfred van...
CASES
2000
ACM
15 years 4 months ago
A first-step towards an architecture tuning methodology for low power
We describe an automated environment to assist a system-on-achip designer to tune a microprocessor core to a particular application program that will run on the microprocessor, an...
Greg Stitt, Frank Vahid, Tony Givargis, Roman L. L...
WSC
2004
15 years 1 months ago
Applying a Cognitive Architecture to Control of Virtual Non-Player Characters
CHI Systems, under contract to the U. S. Army Research Institute, is developing an immersive training system, called Virtual Environment Cultural Training for Operational Readines...
Chris McCollum, Charles Barba, Thomas Santarelli, ...
CCS
2007
ACM
15 years 6 months ago
Analysis of three multilevel security architectures
Various system architectures have been proposed for high assurance enforcement of multilevel security. This paper provides an analysis of the relative merits of three architectura...
Timothy E. Levin, Cynthia E. Irvine, Clark Weissma...
FPL
2009
Springer
107views Hardware» more  FPL 2009»
15 years 4 months ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...