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ISCAS
2008
IEEE
122views Hardware» more  ISCAS 2008»
15 years 9 months ago
A nano-CMOS process variation induced read failure tolerant SRAM cell
— In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...
ISPDC
2008
IEEE
15 years 9 months ago
FPGA Implementations of a Parallel Associative Processor with Multi-Comparand Multi-Search Operations
Multi–comparand associative processors are efficient in parallel processing of complex search problems that arise from many application areas including computational geometry, ...
Zbigniew Kokosinski, Bartlomiej Malus
ICC
2007
IEEE
15 years 9 months ago
Scheduling and Source Control with Average Queue-Length Control in Cellular Networks
— In this paper, a scheduling problem is considered in the cellular network where there exist CBR (constant bit rate) users requiring exact minimum average throughput and delay g...
Hyang-Won Lee, Cheoljung Kim, Song Chong
ICALP
2007
Springer
15 years 9 months ago
Labeling Schemes for Vertex Connectivity
This paper studies labeling schemes for the vertex connectivity function on general graphs. We consider the problem of labeling the nodes of any n-node graph is such a way that gi...
Amos Korman
STACS
2007
Springer
15 years 9 months ago
Compact Forbidden-Set Routing
We study the following problem. Given a weighted planar graph G, assign labels L(v) to vertices so that given L(u), L(v) and L(x) for x ∈ X for any X ⊂ V (G), compute the dist...
Bruno Courcelle, Andrew Twigg