10718 search results - page 126 / 2144 » On the Circuit Implementation Problem |
130
Voted
JCO
2010
15 years 2 months ago
2010
Abstract Polynomial-time data reduction is a classical approach to hard graph problems. Typically, particular small subgraphs are replaced by smaller gadgets. We generalize this ap...
239
Voted
PEPM
2009
ACM
17 years 3 months ago
2009
ACM
The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many ...
106
Voted
ICES
2007
Springer
15 years 9 months ago
2007
Springer
The RISA Architecture is a novel reconfigurable hardware platform containing both hardware and software reconfigurable elements. This paper describes the architecture and the fea...
122
Voted
ASAP
1997
IEEE
15 years 7 months ago
1997
IEEE
This paper presents a method, based on the formalism of affine recurrence equations, for the synthesis of digital circuits exploiting parallelism at the bit-level. In the initial ...
162
Voted
WCE
2007
15 years 4 months ago
2007
- In the speed-independent logic, the hazards caused by input inverters are identified. The known methods of the elimination of such hazards are based on avoiding input inverters. ...