el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...
The electromigration effect within current-density-stressed signal and power lines is an ubiquitous and increasingly important reliability and design problem in sub-micron IC desi...
In this paper, we reviewed several newly presented nonlinear model order reduction methods, we analyze these methods theoretically and with experiments in detail. We show the prob...
The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. In recent years, several approaches have been pro...
We present the first complete problems for dynamic complexity classes including the classes Dyn-FO and Dyn-ThC ¢ , the dynamic classes corresponding to relational calculus and (...