10718 search results - page 153 / 2144 » On the Circuit Implementation Problem |
139
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DATE
2006
IEEE
15 years 7 months ago
2006
IEEE
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
109
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INFSOF
2006
15 years 3 months ago
2006
In finite state machine (FSM) based testing, the problem of fault masking in the unique input/output (UIO) sequence may degrade the test performance of the UIO based methods. This...
CORR
2008
Springer
15 years 3 months ago
2008
Springer
This special session on 3D TSV
130
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CF
2004
ACM
15 years 9 months ago
2004
ACM
Nanoelectronics research has primarily focused on devices. By contrast, not much has been published on innovations at higher layers: we know little about how to construct circuits...
153
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ITC
1994
IEEE
15 years 8 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...