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» On the Circuit Implementation Problem
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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 5 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
DAC
1999
ACM
15 years 8 months ago
Interconnect Analysis: From 3-D Structures to Circuit Models
In this survey paper we describethe combination of: discretized integral formulations, sparsication techniques, and krylov-subspace based model-order reduction that has led to rob...
Mattan Kamon, Nuno Alexandre Marques, Yehia Massou...
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ISCAS
1995
IEEE
66views Hardware» more  ISCAS 1995»
15 years 7 months ago
Damping and Incremental Energy in Thyristor Switching Circuits
: Thyristor controlled reactors provide controllable inductances in utility power lines and are increasingly used for static var control and flexible AC transmission. The size of ...
Rajesh Rajaraman, Ian Dobson
ISMVL
2010
IEEE
209views Hardware» more  ISMVL 2010»
15 years 9 months ago
Secure Design Flow for Asynchronous Multi-valued Logic Circuits
—The purpose of secure devices such as smartcards is to protect secret information against software and hardware attacks. Implementation of the appropriate protection techniques ...
Ashur Rafiev, Julian P. Murphy, Alexandre Yakovlev
ARITH
2005
IEEE
15 years 5 months ago
Quasi-Pipelined Hash Circuits
Hash functions are an important cryptographic primitive. They are used to obtain a fixed-size fingerprint, or hash value, of an arbitrary long message. We focus particularly on ...
Marco Macchetti, Luigi Dadda