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» On the Circuit Implementation Problem
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DT
2002
67views more  DT 2002»
15 years 3 months ago
A Retargetable Embedded In-Circuit Emulation Module for Microprocessors
This article presents an in-circuit emulation (ICE) module that can be embedded with a microprocessr core. The ICE module, based on the IEEE 1149.1 JTAG architecture, supports typ...
Ing-Jer Huang, Chung-Fu Kao, Hsin-Ming Chen, Ching...
GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
15 years 7 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...
145
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VLSISP
2010
148views more  VLSISP 2010»
15 years 2 months ago
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunso...
FCCM
2004
IEEE
152views VLSI» more  FCCM 2004»
15 years 7 months ago
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor
Dynamically Reconfigurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixte...
Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki...
121
Voted
ITC
2003
IEEE
136views Hardware» more  ITC 2003»
15 years 9 months ago
A BIST Solution for The Test of I/O Speed
A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 µ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold...
Cheng Jia, Linda S. Milor