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» On the Circuit Implementation Problem
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DAC
2001
ACM
16 years 5 months ago
Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation
In this paper, we present a new technique for the e cient dynamic detection and removal of inactive clauses, i.e. clauses that do not a ect the solutions of interest of a Boolean ...
Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav A...
STACS
2010
Springer
15 years 10 months ago
Collapsing and Separating Completeness Notions under Average-Case and Worst-Case Hypotheses
This paper presents the following results on sets that are complete for NP. (i) If there is a problem in NP that requires 2nΩ(1) time at almost all lengths, then every many-one N...
Xiaoyang Gu, John M. Hitchcock, Aduri Pavan
ASPDAC
2006
ACM
98views Hardware» more  ASPDAC 2006»
15 years 10 months ago
Timing-driven placement based on monotone cell ordering constraints
− In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed th...
Chanseok Hwang, Massoud Pedram
ISVLSI
2002
IEEE
129views VLSI» more  ISVLSI 2002»
15 years 9 months ago
Accelerating Retiming Under the Coupled-Edge Timing Model
Retiming has been shown to be a powerful technique for improving the performance of synchronous circuits. However, even though retiming algorithms of polynomial time complexity ha...
Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz
FPGA
1997
ACM
127views FPGA» more  FPGA 1997»
15 years 8 months ago
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
Amit Chowdhary, John P. Hayes