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» On the Circuit Implementation Problem
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ISCAS
2002
IEEE
82views Hardware» more  ISCAS 2002»
15 years 9 months ago
Logic synthesis for PLA with 2-input logic elements
In this paper, we present a new logic synthesis method for PLA with 2-input logic elements. A PLA with 2-input logic elements can achieve low-power dissipation and high-speed oper...
Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Ku...
VLSID
1997
IEEE
112views VLSI» more  VLSID 1997»
15 years 8 months ago
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs
An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA ...
James Jacob, P. Srinivas Sivakumar, Vishwani D. Ag...
DAC
2009
ACM
16 years 5 months ago
Handling complexities in modern large-scale mixed-size placement
In this paper, we propose an effective algorithm flow to handle largescale mixed-size placement. The basic idea is to use floorplanning to guide the placement of objects at the gl...
Jackey Z. Yan, Natarajan Viswanathan, Chris Chu
TVLSI
2010
14 years 11 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
DAC
2001
ACM
16 years 5 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis