In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
Model reduction of large-scale linear time-invariant systems is an ubiquitous task in control and simulation of complex dynamical processes. We discuss how LQG balanced truncation ...
The process of design search and optimisation is characterised by its computationally intensive operations, which produce a problem well suited to Grid computing. Here we present a...
Gang Xue, Matt J. Fairman, Graeme E. Pound, Simon ...
This paper presents an algorithm for the automatic mapping of problem specifications to existing architecture templates. The proposed methodology supports the combination of exist...
Nikos S. Voros, Evaggelinos P. Mariatos, Michael K...
We present an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). We use the RTL circuit structure by extending con...
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting...