We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare...
Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Iv...
A parallel implementation of a genetic algorithm used to evolve simple analog VLSI circuits is described. The parallel computer system consisted of twenty distributed SPARC workst...
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
We study the following question, communicated to us by Mikl´os Ajtai: Can all explicit (e.g., polynomial time computable) functions f : ({0, 1}w )3 → {0, 1}w be computed by word...
Kristoffer Arnsfelt Hansen, Oded Lachish, Peter Br...
We investigate the differences in speed between applicationspecific integrated circuits and custom integrated circuits when each are implemented in the same process technology, wi...