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» On the Circuit Implementation Problem
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ICCAD
2003
IEEE
115views Hardware» more  ICCAD 2003»
15 years 6 months ago
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
JPDC
2007
100views more  JPDC 2007»
14 years 9 months ago
Deadlock-free connection-based adaptive routing with dynamic virtual circuits
Virtual circuits can reduce routing overheads with irregular topologies and provide support for a mix of quality of service (QOS) requirements. Information about network loads and...
Yoshio Turner, Yuval Tamir
DAC
1999
ACM
15 years 10 months ago
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminate...
Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton,...
TCAD
2002
128views more  TCAD 2002»
14 years 9 months ago
Preferred direction Steiner trees
Interconnect optimization for VLSI circuits has received wide attention. To model routing surfaces, multiple circuit layers are freabstracted as a single rectilinear plane, ignori...
Mehmet Can Yildiz, Patrick H. Madden
ICCAD
1999
IEEE
86views Hardware» more  ICCAD 1999»
15 years 2 months ago
Clock skew scheduling for improved reliability via quadratic programming
This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadrat...
Ivan S. Kourtev, Eby G. Friedman