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» On the Circuit Implementation Problem
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VTS
1995
IEEE
105views Hardware» more  VTS 1995»
15 years 1 months ago
Cyclic stress tests for full scan circuits
To ensure the production of reliable circuits and fully testable unpackaged dies for MCMs burn-in, both dynamic and monitored, remains a feasible option. During this burn-in proce...
Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Jan...
CODES
2008
IEEE
15 years 4 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid
DATE
1998
IEEE
93views Hardware» more  DATE 1998»
15 years 2 months ago
Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits
We present an integer-linear-programming-based approach for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. It produces the exact so...
Yi-Min Jiang, Kwang-Ting Cheng
ISCAS
2006
IEEE
90views Hardware» more  ISCAS 2006»
15 years 3 months ago
A novel ternary more, less and equality circuit using recharged semi-floating gate devices
— This paper presents a novel Ternary More, Less and Equality (MLE) Circuit implemented with Recharged SemiFloating Gate Transistors. The circuit is a ternary application, and te...
Henning Gundersen, Yngvar Berg
DFT
2003
IEEE
106views VLSI» more  DFT 2003»
15 years 3 months ago
Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits
Transient faults in VLSI circuits could lead to disastrous consequences. With technology scaling, circuits are becoming increasingly vulnerable to transient faults. This papers pr...
Atul Maheshwari, Israel Koren, Wayne Burleson