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RECONFIG
2009
IEEE
269views VLSI» more  RECONFIG 2009»
15 years 10 months ago
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices
Abstract—Integrated circuits for very high-speed telecommunication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGA...
Guilherme Guindani, Frederico Ferlini, Jeferson Ol...
100
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ISW
2001
Springer
15 years 7 months ago
Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator B
In this paper, we present the results of the first phase of a project aimed at implementing a full suite of IPSec cryptographic transformations in reconfigurable hardware. Full imp...
Pawel Chodowiec, Kris Gaj, Peter Bellows, Brian Sc...
FPL
2001
Springer
136views Hardware» more  FPL 2001»
15 years 8 months ago
Building Asynchronous Circuits with JBits
Asynchronous logic design has been around for decades. However, only recently has it gained any commercial success. Research has focused on a wide variety of uses, from microproces...
Eric Keller
ARVLSI
2001
IEEE
289views VLSI» more  ARVLSI 2001»
15 years 7 months ago
A High-Performance 64-bit Adder Implemented in Output Prediction Logic
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
Sheng Sun, Larry McMurchie, Carl Sechen
COMCOM
2006
154views more  COMCOM 2006»
15 years 3 months ago
Wireless sensor networks for personal health monitoring: Issues and an implementation
Recent technological advances in sensors, low-power integrated circuits, and wireless communications have enabled the design of lowcost, miniature, lightweight, and intelligent ph...
Aleksandar Milenkovic, Chris Otto, Emil Jovanov