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» On the Circuit Implementation Problem
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136
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TPHOL
1999
IEEE
15 years 7 months ago
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
Combining theorem proving and model checking o ers the tantalizing possibility of e ciently reasoning about large circuits at high levels of abstraction. We have constructed a syst...
Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger
125
Voted
FPL
2009
Springer
166views Hardware» more  FPL 2009»
15 years 8 months ago
Modeling post-techmapping and post-clustering FPGA circuit depth
This paper presents an analytical model that relates FPGA architectural parameters to the expected speed of FPGA implementation. More precisely, the model relates the lookuptable ...
Joydip Das, Steven J. E. Wilton, Philip Heng Wai L...
100
Voted
VTS
2000
IEEE
97views Hardware» more  VTS 2000»
15 years 7 months ago
A Low-Speed BIST Framework for High-Performance Circuit Testing
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to...
Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev
VLSID
2002
IEEE
107views VLSI» more  VLSID 2002»
16 years 3 months ago
Estimation of Maximum Power-Up Current
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
Fei Li, Lei He, Kewal K. Saluja
DFT
2007
IEEE
101views VLSI» more  DFT 2007»
15 years 9 months ago
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits
Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, vari...
Francesco Regazzoni, Thomas Eisenbarth, Johann Gro...