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» On the Circuit Implementation Problem
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128
Voted
ACSD
2003
IEEE
105views Hardware» more  ACSD 2003»
15 years 7 months ago
Detecting State Coding Conflicts in STG Unfoldings Using SAT
Abstract. The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling...
Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
DAC
2005
ACM
15 years 5 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...
156
Voted
TODAES
2008
158views more  TODAES 2008»
15 years 3 months ago
Designing secure systems on reconfigurable hardware
The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integ...
Ted Huffmire, Brett Brotherton, Nick Callegari, Jo...
110
Voted
ASPDAC
2000
ACM
102views Hardware» more  ASPDAC 2000»
15 years 7 months ago
Multi-clock path analysis using propositional satisfiability
We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to re...
Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, ...
STOC
1989
ACM
96views Algorithms» more  STOC 1989»
15 years 7 months ago
Optimal Size Integer Division Circuits
Division is a fundamental problem for arithmetic and algebraic computation. This paper describes Boolean circuits of bounded fan-in for integer division  nding reciprocals that...
John H. Reif, Stephen R. Tate