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» On the Circuit Implementation Problem
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125
Voted
SBCCI
2006
ACM
126views VLSI» more  SBCCI 2006»
15 years 9 months ago
Power constrained design optimization of analog circuits based on physical gm/ID characteristics
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
Alessandro Girardi, Sergio Bampi
PDP
2003
IEEE
15 years 8 months ago
A Parallel Evolutionary Algorithm for Circuit Partitioning
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimi...
Raul Baños, Consolación Gil, Maria D...
156
Voted
TCAD
2008
96views more  TCAD 2008»
15 years 3 months ago
An Implicit Approach to Minimizing Range-Equivalent Circuits
Abstract--Simplifying a combinational circuit while preserving its range has a variety of applications, such as combinational equivalence checking and random simulation. Previous a...
Yung-Chih Chen, Chun-Yao Wang
DAC
2001
ACM
16 years 4 months ago
Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems
This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the rst implementation incorporates a ...
Jafar Savoj, Behzad Razavi
99
Voted
EH
2003
IEEE
116views Hardware» more  EH 2003»
15 years 8 months ago
Silicon Validation of Evolution-Designed Circuits
No silicon fabrication and characterization of circuits with topologies designed by evolution has been done before, leaving open questions about the feasibility of the evolutionar...
Adrian Stoica, Ricardo Salem Zebulum, Xin Guo, Did...