This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimi...
Abstract--Simplifying a combinational circuit while preserving its range has a variety of applications, such as combinational equivalence checking and random simulation. Previous a...
This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the rst implementation incorporates a ...
No silicon fabrication and characterization of circuits with topologies designed by evolution has been done before, leaving open questions about the feasibility of the evolutionar...
Adrian Stoica, Ricardo Salem Zebulum, Xin Guo, Did...