Sciweavers

1795 search results - page 224 / 359
» On the Complexity of Circuit Satisfiability
Sort
View
ISPD
2003
ACM
103views Hardware» more  ISPD 2003»
15 years 6 months ago
An integrated floorplanning with an efficient buffer planning algorithm
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, ...
COMPGEOM
2010
ACM
15 years 6 months ago
Output-sensitive algorithm for the edge-width of an embedded graph
Let G be an unweighted graph of complexity n cellularly embedded in a surface (orientable or not) of genus g. We describe improved algorithms to compute (the length of) a shortest...
Sergio Cabello, Éric Colin de Verdiè...
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
15 years 5 months ago
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis
— Memory is one of the most important components to be optimized in the several phases of the synthesis process. ioral synthesis, a memory is viewed as an abstract construct whic...
Gernot Koch, Taewhan Kim, Reiner Genevriere
ARVLSI
1999
IEEE
162views VLSI» more  ARVLSI 1999»
15 years 5 months ago
Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking Chip
The ability of animals to select a limited region of sensory space for scrutiny is an important factor in dealing with cluttered or complex sensory environments. Such an attention...
Timothy K. Horiuchi, Ernst Niebur
FASE
2000
Springer
15 years 4 months ago
Parallel Refinement Mechanisms for Real-Time Systems
This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and f...
Paul Z. Kolano, Richard A. Kemmerer, Dino Mandriol...