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» On the Complexity of Circuit Satisfiability
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ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
15 years 6 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
113
Voted
ISLPED
2003
ACM
129views Hardware» more  ISLPED 2003»
15 years 6 months ago
A critical analysis of application-adaptive multiple clock processors
Enabled by the continuous advancement in fabrication technology, present day synchronous microprocessors include more than 100 million transistors and have clock speeds well in ex...
Emil Talpes, Diana Marculescu
102
Voted
ISCAS
2002
IEEE
153views Hardware» more  ISCAS 2002»
15 years 5 months ago
Biological learning modeled in an adaptive floating-gate system
We have implemented an aspect of learning and memory in the nervous system using analog electronics. Using a simple synaptic circuit we realize networks with Hebbian type adaptati...
Christal Gordon, Paul E. Hasler
FOCS
1999
IEEE
15 years 5 months ago
Near-Optimal Conversion of Hardness into Pseudo-Randomness
Various efforts ([?, ?, ?]) have been made in recent years to derandomize probabilistic algorithms using the complexity theoretic assumption that there exists a problem in E = dti...
Russell Impagliazzo, Ronen Shaltiel, Avi Wigderson
96
Voted
FP
1989
124views Formal Methods» more  FP 1989»
15 years 4 months ago
Deriving the Fast Fourier Algorithm by Calculation
This paper reports an explanation of an intricate algorithm in the terms of a potentially mechanisable rigorous-development method. It uses notations and techniques of Sheeran 1] ...
Geraint Jones