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HPCA
2006
IEEE
16 years 2 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
HPCA
2005
IEEE
16 years 2 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
HPCA
2004
IEEE
16 years 2 months ago
Out-of-Order Commit Processors
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
Adrián Cristal, Daniel Ortega, Josep Llosa,...
CHI
2004
ACM
16 years 2 months ago
Master usability scaling: magnitude estimation and master scaling applied to usability measurement
Master Usability Scaling (MUS) is a measurement method for developing a universal usability continuum based on magnitude estimation and master scaling. The universal usability con...
Mick McGee
CHI
2003
ACM
16 years 2 months ago
Leaders leading? a shift in technology adoption
In the past, most early hands-on users of interactive software in organizations were individual contributors. Managers as early adopters is a new trend with significant implicatio...
Jonathan Grudin
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