155 search results - page 7 / 31 » On the Expressive Power of Deep Architectures |
ASPDAC
2009
ACM
15 years 1 months ago
2009
ACM
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
ANCS
2007
ACM
15 years 1 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
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ANCS
2007
ACM
15 years 1 months ago
2007
ACM
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
AHS
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmabl...