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» On the Expressive Power of Deep Architectures
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TCOM
2010
69views more  TCOM 2010»
14 years 8 months ago
Per-antenna rate and power control for MIMO layered architectures in the low- and high-power regimes
—In a MIMO layered architecture, several codewords are transmitted from a multiplicity of antennas. Although the spectral efficiency is maximized if the rates of these codewords...
Angel Lozano
82
Voted
DAC
2003
ACM
15 years 2 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
IPSN
2005
Springer
15 years 3 months ago
XYZ: a motion-enabled, power aware sensor node platform for distributed sensor network applications
— This paper describes the XYZ, a new open-source sensing platform specifically designed to support our experimental research in mobile sensor networks. The XYZ node is designed...
Dimitrios Lymberopoulos, Andreas Savvides
81
Voted
DAC
2002
ACM
15 years 10 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
15 years 2 months ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli