On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
In this paper, we try to demonstrate the capability of a very simple architecture to learn to recognize and reproduce facial expressions without the innate capability to recognize ...
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
In this paper, we propose a novel simulation algorithm for large scale structured power grid networks. The new method formulates the traditional linear system as a special two-dim...
Jin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon ...
— Digital signal processing applications often require the computation of linear systems. These computations can be considerably expensive and require optimizations for lower pow...
Arash Arfaee, Ali Irturk, Nikolay Laptev, Farzan F...