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» On the Expressive Power of Deep Architectures
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TC
2008
14 years 9 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
69
Voted
DAGSTUHL
2003
14 years 11 months ago
Toward a Cognitive System Algebra: Application to Facial Expression Learning and Imitation
In this paper, we try to demonstrate the capability of a very simple architecture to learn to recognize and reproduce facial expressions without the innate capability to recognize ...
Philippe Gaussier, Ken Prepin, Jacqueline Nadel
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
14 years 9 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
DAC
2009
ACM
15 years 26 days ago
GPU friendly fast Poisson solver for structured power grid network analysis
In this paper, we propose a novel simulation algorithm for large scale structured power grid networks. The new method formulates the traditional linear system as a special two-dim...
Jin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon ...
DAC
2009
ACM
15 years 2 months ago
Xquasher: a tool for efficient computation of multiple linear expressions
— Digital signal processing applications often require the computation of linear systems. These computations can be considerably expensive and require optimizations for lower pow...
Arash Arfaee, Ali Irturk, Nikolay Laptev, Farzan F...