8780 search results - page 1582 / 1756 » On the Feasibility of Consistent Computations |
ICCAD
2004
IEEE
15 years 7 months ago
2004
IEEE
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
87
Voted
ICCAD
2001
IEEE
15 years 7 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
100
click to vote
CVPR
2010
IEEE
15 years 5 months ago
2010
IEEE
Piecewise planar models for stereo have recently become popular for modeling indoor and urban outdoor scenes. The strong planarity assumption overcomes the challenges presented by...
79
Voted
STACS
2010
Springer
15 years 5 months ago
2010
Springer
We show that the Tile Assembly Model exhibits a strong notion of universality where the goal is to give a single tile assembly system that simulates the behavior of any other tile...
STACS
2010
Springer
15 years 5 months ago
2010
Springer
Abstract. A Boolean function on N variables is called evasive if its decision-tree complexity is N. A sequence Bn of Boolean functions is eventually evasive if Bn is evasive for al...