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» On the Formal Generation of Process Redesigns
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COLING
1990
15 years 28 days ago
A Type-theoretical Analysis of Complex Verb Generation
Tense and aspect, together with mood and modality, usually form the entangled structure of a complex verb. They are often hard to translate by machines, because of both syntactic ...
Satoshi Tojo
FDL
2007
IEEE
15 years 6 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
ICAC
2005
IEEE
15 years 5 months ago
The J3 Process for Building Autonomic Enterprise Java Bean Systems
Autonomic computer systems aim to reduce the configuration, operational, and maintenance costs of distributed enterprise applications. This paper provides two contributions to the...
Jules White, Douglas C. Schmidt, Aniruddha S. Gokh...
93
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WSC
1998
15 years 1 months ago
Validation and Verification of the Simulation Model of a Photolithography Process in Semiconductor Manufacturing
Simulation modeling provides an effective and powerful approach for capturing and analyzing complex manufacturing systems. More and more decisions are based on computer generated ...
Nirupama Nayani, Mansooreh Mollaghasemi
TSE
2010
155views more  TSE 2010»
14 years 10 months ago
A Comparison of Six UML-Based Languages for Software Process Modeling
— Describing and managing activities, resources and constraints of software development processes is a challenging goal for many organizations. A first generation of Software Pro...
Reda Bendraou, Jean-Marc Jézéquel, M...