Sciweavers

281 search results - page 46 / 57
» On the Hardware Implementation Cost of Crypto-Processors Arc...
Sort
View
IPPS
2006
IEEE
15 years 4 months ago
Bio-sequence database scanning on a GPU
Protein sequences with unknown functionality are often compared to a set of known sequences to detect functional similarities. Efficient dynamic programming algorithms exist for t...
Weiguo Liu, Bertil Schmidt, Gerrit Voss, Adrian Sc...
SC
1995
ACM
15 years 1 months ago
A Performance Evaluation of the Convex SPP-1000 Scalable Shared Memory Parallel Computer
The Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical s...
Thomas L. Sterling, Daniel Savarese, Peter MacNeic...
82
Voted
MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
15 years 2 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin
ARITH
2001
IEEE
15 years 2 months ago
Computer Arithmetic-A Processor Architect's Perspective
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
Ruby B. Lee
EGH
2004
Springer
15 years 3 months ago
Realtime ray tracing of dynamic scenes on an FPGA chip
Realtime ray tracing has recently established itself as a possible alternative to the current rasterization approach for interactive 3D graphics. However, the performance of exist...
Jörg Schmittler, Sven Woop, Daniel Wagner, Wo...