Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
Alexander B. Smirnov, Alexander Taubin, Ming Su, M...
The rapid development of Internet makes network management on large-scale network a critical issue. But with the management task of large-scale network becoming more complicated, ...
We present a discrete-event network simulator, called Simnet, designed specifically for analyzing networksecurity protocols. The design and implementation is focused on simplicit...
Seny Kamara, Darren Davis, Lucas Ballard, Ryan Cau...
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
Konrad J. Kulikowski, Ming Su, Alexander B. Smirno...
We propose a mechanism for providing the incentives for reporting truthful feedback in a peer-to-peer system for exchanging services. This mechanism is to complement reputation me...