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» On the Inertia of the Asynchronous Circuits
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ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
15 years 4 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
CHARME
1995
Springer
120views Hardware» more  CHARME 1995»
15 years 3 months ago
Timing analysis of asynchronous circuits using timed automata
In this paper we present a method formodeling asynchronous digital circuits by timed automata. The constructed timed automata serve as \mechanical" and veri able objects for a...
Oded Maler, Amir Pnueli
ASYNC
2005
IEEE
132views Hardware» more  ASYNC 2005»
15 years 5 months ago
High Level Synthesis of Timed Asynchronous Circuits
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, C...
IJCNN
2000
IEEE
15 years 4 months ago
Hardware Implementation of a PCA Learning Network by an Asynchronous PDM Digital Circuit
We have fabricated a PCA (Principal Component Analysis) learning network in a FPGA (Field Programmable Gate Array) by using an asynchronous PDM (Pulse Density Modulation) digital ...
Yuzo Hirai, Kuninori Nishizawa
ICCAD
1998
IEEE
83views Hardware» more  ICCAD 1998»
15 years 3 months ago
Lazy transition systems: application to timing optimization of asynchronous circuits
This paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzT...
Jordi Cortadella, Michael Kishinevsky, Alex Kondra...