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» On the Inertia of the Asynchronous Circuits
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FPGA
2005
ACM
158views FPGA» more  FPGA 2005»
15 years 7 months ago
Automated synthesis for asynchronous FPGAs
We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-leve...
Song Peng, David Fang, John Teifel, Rajit Manohar
VLSID
1999
IEEE
91views VLSI» more  VLSID 1999»
15 years 6 months ago
Timed Circuit Synthesis Using Implicit Methods
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...
Robert Thacker, Wendy Belluomini, Chris J. Myers
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
15 years 7 months ago
AER EAR: a matched silicon cochlea pair with address event representation interface
In this paper we present an analog integrated circuit containing a matched pair of silicon cochleae and an address event interface. Each section of the cochlea, modeled by a secon...
André van Schaik, Shih-Chii Liu
DSD
2010
IEEE
133views Hardware» more  DSD 2010»
14 years 11 months ago
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
Igor Lemberski, Petr Fiser
ISMVL
2005
IEEE
86views Hardware» more  ISMVL 2005»
15 years 7 months ago
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders
A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in Low-Density Parity-Check (LDPC) decoders, where high-throughput ...
Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu