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» On the Inertia of the Asynchronous Circuits
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ACSD
2005
IEEE
90views Hardware» more  ACSD 2005»
15 years 7 months ago
Improved Decomposition of STGs
Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous circuit behaviour. It has been suggested to decompose such a specification as a...
Walter Vogler, Ben Kangsah
103
Voted
ASYNC
2002
IEEE
115views Hardware» more  ASYNC 2002»
15 years 6 months ago
Point to Point GALS Interconnect
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
George S. Taylor, Simon W. Moore, Robert D. Mullin...
LICS
1996
IEEE
15 years 6 months ago
Reactive Modules
We present a formal model for concurrent systems. The model represents synchronous and asynchronous components in a uniform framework that supports compositional (assume-guarantee)...
Rajeev Alur, Thomas A. Henzinger
ASPDAC
2004
ACM
144views Hardware» more  ASPDAC 2004»
15 years 5 months ago
Verification of timed circuits with symbolic delays
When time is incorporated in the specification of discrete systems, the complexity of verification grows exponentially. When the temporal behavior is specified with symbols, the ve...
Robert Clarisó, Jordi Cortadella
DAC
1999
ACM
15 years 6 months ago
A Practical Approach to Multiple-Class Retiming
Retiming is an optimization technique for synchronous circuits introduced by Leiserson and Saxe in 1983. Although powerful, retiming is not very widely used because it does not ha...
Klaus Eckl, Jean Christophe Madre, Peter Zepter, C...